1. Field of the Invention
This invention relates to an improved composition of slurries, a process for the chemical mechanical polishing or planarization of semiconductor wafers and to semiconductor wafers made according the foregoing process.
2. Description of the Prior Art
During integrated circuit manufacture, semiconductor wafers used in semiconductor fabrication typically undergo numerous processing steps, including deposition, patterning, and etching steps. Details of these manufacturing steps for semiconductor wafers are reported by Tonshoff et al., “Abrasive Machining of Silicon”, published in the Annals of the International Institution for Production Engineering Research, (Volume 39/2/1990), pp. 621-635. In each manufacturing step, it is often necessary or desirable to modify or refine an exposed surface of the wafer in order to prepare the wafer for subsequent fabrication or manufacturing steps. In conventional semiconductor device fabrication schemes, a silicon wafer is subjected to numerous processing steps that deposit uniform layers of two or more discrete materials which together form a single layer of what will become a multi-layer structure. In this process, it is common to apply a uniform layer of a first material to the wafer itself or to an existing layer of an intermediate constructed by any of the means commonly employed in the art, to etch features into or through that layer, and then to fill the features with a second material. Alternatively, features of approximately uniform thickness comprising a first material may be deposited onto the wafer, or onto a previously fabricated layer of the wafer, usually through a mask, and then the regions adjacent to those features may be filled with a second material to complete the layer. Following the deposition step, the deposited material or layer on a wafer surface generally needs further processing before additional deposition or subsequent processing occurs. When completed, the outer surface is substantially globally planar and parallel to the base silicon wafer surface. A specific example of such a process is the Damascene processes.
In the Damascene process, a pattern is etched into an oxide dielectric (e.g., SiO2) layer. After etching, optional adhesion and or barrier layers are deposited over the oxide surface. Typical barrier layers may include tantalum, tantalum nitride, titanium nitride or titanium, or tungsten. Next, a metal (e.g., copper) is deposited over or on top of the adhesion and or barrier layers. The copper metal layer is then modified, refined or finished by removing the copper metal and regions of the adhesion and or barrier layer on the surface of the underlying dielectric. Typically, enough surface metal is removed so that the outer exposed surface of the wafer comprises both metal and an oxide dielectric material. A top view of the exposed wafer surface would reveal a planar surface with copper metal corresponding to the etched pattern and barrier layer or dielectric material adjacent to the copper metal. The copper (or other metal) and oxide dielectric material(s) located on the modified surface of the wafer inherently have different hardness values and susceptibly to controlled corrosion. The method to modify the surface of the semiconductor may be a combination of a physical and chemical process. Such a process is called chemical mechanical planarization (CMP). An abrasive CMP process used to modify a wafer produced by the Damascene process must be designed to simultaneously modify the metal (e.g., copper) and barrier layer or dielectric materials without inducing defects in the surface of either material. The abrasive process must create a planar outer exposed surface on a wafer having an exposed area of a metal and an exposed area of a dielectric material.
Chemical mechanical polishing (or planarization) (CMP) is an area in semiconductor processing undergoing rapid changes. CMP provides global (millimeter-sized dimensions) and local (micron to nanoscale-sized) planarization on the wafer surface. This planarity improves the coverage of the wafer with dielectric materials and metals (e.g., copper) and increases lithography, etching and deposition process latitudes. Various equipment companies are advancing CMP technology through improvements in the engineering aspects of CMP while chemical companies are focusing on consumables such as slurries and polishing pads. For example, conventional CMP methods for modifying or refining exposed surfaces of structured wafers uses techniques that polish a wafer surface with a slurry containing a plurality of loose abrasive particles dispersed in an aqueous medium. Typically this slurry is applied to a polishing pad and the wafer surface is rotated against the pad in order to remove the desired material from the wafer surface. Generally, the slurry may also contain chemical agents that react with the wafer surface to enhance metal removal rates.
A relatively new alternative to CMP slurry methods uses an abrasive pad to planarize a semiconductor surface and thereby eliminate the need for the foregoing slurries containing polishing particles. This alternative CMP process is reported in International Publication No. WO 97/11484, published Mar. 27, 1997. The abrasive pad has a textured abrasive surface which includes abrasive particles dispersed in a binder. During polishing, the abrasive pad is contacted with a semiconductor wafer surface, often in the presence of a working slurry containing no additional abrasive particles. The aqueous slurry is applied to the surface of the wafer to chemically modify or enhance the removal of a material from the surface of the wafer under the action of the abrasive article.
Working slurries useful in the process described above, either in conjunction with the aforementioned slurries or the abrasive pad, are typically aqueous solutions of a variety of additives including metal complexing agents, oxidizing agents, passivating agents, surfactants, wetting agents, buffers, viscosity modifiers or combinations of these additives. Additives may also include agents which are reactive with the second material, e.g., metal or metal alloy conductors on the wafer surface such as oxidizing, reducing, passivating, or complexing agents. Examples of such working slurries may be found, for example, in U.S. patent application Ser. No. 09/091,932 filed Jun. 24, 1998.
Variables that may affect wafer CMP processing include the selection of the contact pressure between the wafer surface and abrasive article, composition of the polishing pad, use of a sub-polishing pad, geometry of the grooves in the polishing pad, type of slurry medium, relative speed and relative motion between the wafer surface and the abrasive article, and the flow rate of the slurry medium. These variables are interdependent, and are selected based upon the individual metal surface being polished.
CMP processes for modifying the deposited metal layer until the barrier layer or oxide dielectric material is exposed on the wafer outer surface leaves little margin for error because of the sub-micron dimensions of the metal features found on the wafer surface. The removal rate of the deposited metal should be relatively fast to minimize the need for additional expensive CMP tools, and the metal must be completely removed from the areas that were not etched. The metal remaining in the etched areas must be limited to discrete areas while being continuous within those areas or zones to ensure proper conductivity. Thus, the CMP process must be uniform, controlled, and reproducible on a sub-micron to nano-scale dimension.
In the CMP processes mentioned above, dishing performance, scratches or defects and removal rate of the metal are measurements of CMP performance. These performance measurements may depend on the use of the foregoing working slurries and mechanical polishing processes. Dishing is a measure of how much metal, such as copper, is removed from bond pads or wire traces below the plane of the intermediate wafer surface as defined by the difference in height between the copper and the tops of-the barrier or dielectric layers following removal of the blanket copper or copper plus barrier layer. Removal rate refers to the amount of material removed per unit time. Removal rates greater than at least about 1000 A per minute are preferred. Lower removal rates, such as a few hundred angstroms per minute (A/min) or less, are less desirable because they tend to create increases in the overall manufacturing costs (cost of ownership) associated with wafer manufacture.
To lower the propensity for dishing and increase metal removal rates on semiconductor devices, it is important to design slurries with components in fairly narrow concentration ranges and pH values. The pH of the slurries used in polishing of semiconductor devices is dependent upon the composition of the surface layer to be polished. In most cases, it is necessary to engineer a slurry with a proper pH to effectively produce an oxide layered surface at the same rate the mechanical action of abrasion removes this metal oxide. For example, in polishing dielectric materials such as SiO2, the pH of the slurry is typically >10 to assist in the formation of silanol bonds:
SiO2 + 2H2O <→ Si(OH)4(aq)pH < 9Si(OH)4(aq) + OH—→ SiO(OH)3 + H2OpH > 9SiO(OH)3 → polynuclear speciespH > 10.52Si(OH)4(aq) → (HO)3Si—O—Si(OH)3 + H20
The pH of the SiO2 polishing slurries must be greater than 10 to ensure rapid formation of the silicon dioxide after mechanically polishing the surface.
For copper polishing slurries, U.S. Pat. No. 6,117,783 shows the importance of pH of about 6.0 to form a copper(l) oxide, Cu2O. Cuprous oxide can form only in near-neutral to slightly basic media. In low pH slurries, a protective oxide may not form on the copper surface thus increasing the propensity for aggressive attack by the oxidizing agent on copper metal. In high pH slurries, removed copper may precipitate from solution resulting in un-wanted particulate matter adhering to the wafer surface. Therefore, copper polishing slurries must be formulated within a narrow pH window to ensure a high yield after CMP.
Another important area is to understand with regard to pH control and, if possible, to adjust the slurries is the Zeta potential. The Zeta potential is a electrostatic potential measurement of the interaction of the electrically charged double layer ions of anions and cations that surround the inorganic polishing particles in a slurry. The Zeta potential is dependent upon the nature of the polishing particle (e.g., Al2O3, CeO2, SiO2 etc.) and the slurry pH. Slurries that exhibit an undesired Zeta potential are typically unstable and as a result the particles may settle from the slurry or agglomerate. This can be very detrimental to its performance during the CMP polishing process.
Another measure of Zeta potential is the isoelectric point (IEP) for the polishing particles. The IEP is the pH at which the Zeta potential value is zero. The chemical composition and nature of the particles can have significant effects on the IEP. Some selected values of the IEP are: aluminum oxide particles can vary from 3.8 to 9.4, while silicon oxide has a narrower range 1.5 to 3.7.
Some metal oxides IEP values are 9.5 for TiO, while for that of pure tungsten is somewhere around about 1. Such wide ranges of IEP values pose a major challenge to developing chemistries to control the Zeta potential of the particles that may eventually adhere to the wafer surface. Additionally, the Zeta potential between the polishing particles and the wafer may be that the particles will be attracted and adhere to the wafer surface which in turn requires that a post CMP clean step is required to remove the adhering particles.
It is therefore critical to maintain the Zeta potential in a given range by holding the pH of the slurry constant during CMP.
It is desirable to provide improvements in chemical mechanical planarization by providing working slurries useful in modifying exposed intermediate surfaces of structured wafers for semiconductor fabrication and to methods of modifying the exposed intermediate surfaces of such wafers for semiconductor fabrication, preferably with improved, sustainable, metal removal rates and utilizing the foregoing family of working slurries. It is especially desirable to provide working slurries that are more stable than commercially available slurries. It is also desirable to provide working slurries that are useful in the aforementioned methods and resulting in the fabrication of metal containing structured wafers with better planarity and less defects.